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ARD2
1.00 for Rev B. Hardware
Airbag Reference Demonstrator using MPC5604P
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00001 00017 #ifndef _EDMA_H 00018 #define _EDMA_H 00019 00020 /* 00021 ****************************************************************************** 00022 * Defines, Macros and Typedefs 00023 *****************************************************************************/ 00024 /*** Constant Macros ***/ 00025 /* Default Yes and No defines */ 00026 #ifndef TRUE 00027 #define TRUE (1u) 00028 #endif 00029 #ifndef CLEAR 00030 #define CLEAR (0u) 00031 #endif 00032 #ifndef BITS_IN_NIBBLE 00033 #define BITS_IN_NIBBLE (4u) 00034 #endif 00035 #ifndef BITS_IN_BYTE 00036 #define BITS_IN_BYTE (8u) 00037 #endif 00038 #ifndef BITS_IN_32 00039 #define BITS_IN_32 (32u) 00040 #endif 00041 #ifndef BITS_IN_16 00042 #define BITS_IN_16 (16u) 00043 #endif 00044 #ifndef BYTES_IN_32 00045 #define BYTES_IN_32 (4u) 00046 #endif 00047 #ifndef BYTES_IN_16 00048 #define BYTES_IN_16 (2u) 00049 #endif 00050 #ifndef BIT_DEFINITION 00051 #define BIT_DEFINITION 00052 #define BIT0 (1u << 0u) 00053 #define BIT1 (1u << 1u) 00054 #define BIT2 (1u << 2u) 00055 #define BIT3 (1u << 3u) 00056 #define BIT4 (1u << 4u) 00057 #define BIT5 (1u << 5u) 00058 #define BIT6 (1u << 6u) 00059 #define BIT7 (1u << 7u) 00060 #define BIT8 (1u << 8u) 00061 #define BIT9 (1u << 9u) 00062 #define BIT10 (1u << 10) 00063 #define BIT11 (1u << 11) 00064 #define BIT12 (1u << 12) 00065 #define BIT13 (1u << 13) 00066 #define BIT14 (1u << 14) 00067 #define BIT15 (1u << 15) 00068 #define BIT16 (1u << 16) 00069 #define BIT17 (1u << 17) 00070 #define BIT18 (1u << 18) 00071 #define BIT19 (1u << 19) 00072 #define BIT20 (1u << 20) 00073 #define BIT21 (1u << 21) 00074 #define BIT22 (1u << 22) 00075 #define BIT23 (1u << 23) 00076 #define BIT24 (1u << 24) 00077 #define BIT25 (1u << 25) 00078 #define BIT26 (1u << 26) 00079 #define BIT27 (1u << 27) 00080 #define BIT28 (1u << 28) 00081 #define BIT29 (1u << 29) 00082 #define BIT30 (1u << 30) 00083 #define BIT31 (1u << 31) 00084 #endif 00085 00086 /* For config */ 00087 #define CHANNEL_TO_CHANNEL_LINKING_ON_MAJOR_LOOP_EN (0x80000000u) 00088 #define CHANNEL_TO_CHANNEL_LINKING_ON_MAJOR_LOOP_DIS (0x00000000u) 00089 #define CHANNEL_TO_CHANNEL_LINKING_ON_MINOR_LOOP_EN (0x80000000u) 00090 #define CHANNEL_TO_CHANNEL_LINKING_ON_MINOR_LOOP_DIS (0x00000000u) 00091 #define DMA_8_BIT_SOURCE (0x00000000u) 00092 #define DMA_16_BIT_SOURCE (0x01000000u) 00093 #define DMA_32_BIT_SOURCE (0x02000000u) 00094 #define DMA_64_BIT_SOURCE (0x03000000u) 00095 #define DMA_8_BIT_TARGET (0x00000000u) 00096 #define DMA_16_BIT_TARGET (0x00010000u) 00097 #define DMA_32_BIT_TARGET (0x00020000u) 00098 #define DMA_64_BIT_TARGET (0x00030000u) 00099 #define DONT_STALL_DMA (0x00000000u) 00100 #define STALL_DMA_4_CYCLES (0x00008000u) 00101 #define STALL_DMA_8_CYCLES (0x0000C000u) 00102 #define DMA_ISR_HALF_WAY_THROUGH (0x00000004u) 00103 #define DMA_ISR_WHEN_DONE (0x00000002u) 00104 #define DMA_START (0x00000001u) 00105 00106 #define DMA_SIZE_8_BIT (0x00u) 00107 #define DMA_SIZE_16_BIT (0x01u) 00108 #define DMA_SIZE_32_BIT (0x02u) 00109 #define DMA_SIZE_64_BIT (0x03u) 00110 #define DMA_BWC_NONE (0x00u) 00111 #define DMA_BWC_4_CYCLE_STALL (0x02u) 00112 #define DMA_BWC_8_CYCLE_STALL (0x03u) 00113 00114 /* For Mux Config */ 00115 #define DMA_MUX_ENABLED (0x80u) 00116 #define DMA_MUX_DISABLED (0x00u) 00117 #define DMA_TRIGGER_ENABLED (0x40u) 00118 #define DMA_TRIGGER_DISABLED (0x00u) 00119 00120 /*** Function Macros ***/ 00121 #ifndef N_ELEMENTS 00122 #define N_ELEMENTS(X) (sizeof(X)/sizeof(*(X))) 00123 #endif 00124 00125 #define CURRENT_MAJOR_ITERATION(xx) ((uint32_t)((xx) << 16u)) 00126 #define DMA_OFFSET(xx) ((uint32_t)(xx)) 00127 #define NUMBER_OF_MAJOR_ITERATIONS(xx) ((uint32_t)((xx) << 16u)) 00128 #define DMA_CLEAR_ISR_FLAG(XX) EDMA.CIRQR.R = XX 00129 #define DMA_MUX_ENABLE(XX, YY) DMAMUX.CHCONFIG[XX].B.ENBL = YY 00130 /*** Enums ***/ 00131 enum DMA_CHANNEL_STATE 00132 { 00133 DMA_SERVICE_REQUEST_ASSERTED, DMA_EXECUTING, DMA_COMPLETED_MINOR_LOOP, 00134 DMA_COMPLETED_MAJOR_LOOP 00135 }; 00136 enum DMA_MUX_SOURCES 00137 { 00138 DMA_SOURCE_DSPI0_TX = 1, DMA_SOURCE_DSPI0_RX, DMA_SOURCE_DSPI1_TX, 00139 DMA_SOURCE_DSPI1_RX, DMA_SOURCE_DSPI2_TX, DMA_SOURCE_DSPI2_RX, 00140 DMA_SOURCE_DSPI3_TX, DMA_SOURCE_DSPI3_RX, DMA_SOURCE_CTU, DMA_SOURCE_FIF01, 00141 DMA_SOURCE_FIFO2, DMA_SOURCE_FIFO3, DMA_SOURCE_FIFO4, DMA_SOURCE_FLEX_PWM_WR, 00142 DMA_SOURCE_FLEX_PWM_RD, DMA_SOURCE_ETIMER0_CH0, DMA_SOURCE_ETIMER0_CH1, 00143 DMA_SOURCE_ETIMER1_CH0, DMA_SOURCE_ETIMER1_CH1, DMA_SOURCE_ADC0, 00144 DMA_SOURCE_ADC1, DMA_SOURCE_ALWAYS 00145 }; 00146 /*** TypeDefs ***/ 00147 typedef __attribute__(( aligned(32) )) union 00148 { 00149 struct 00150 { 00151 uint32_t SADDR; /* source address */ 00152 uint16_t SMOD :5; /* source address modulo */ 00153 uint16_t SSIZE :3; /* source transfer size */ 00154 uint16_t DMOD :5; /* destination address modulo */ 00155 uint16_t DSIZE :3; /* destination transfer size */ 00156 int16_t SOFF; /* signed source address offset */ 00157 uint32_t NBYTES; /* inner (“minor”) byte count */ 00158 int32_t SLAST; /* last destination address adjustment, or */ 00159 /* scatter/gather address (if e_sg = 1) */ 00160 uint32_t DADDR; /* destination address */ 00161 uint16_t CITERE_LINK :1; 00162 uint16_t CITER :15; 00163 int16_t DOFF; /* signed destination address offset */ 00164 int32_t DLAST_SGA; 00165 uint16_t BITERE_LINK :1; /* beginning ("major") iteration count */ 00166 uint16_t BITER :15; 00167 uint16_t BWC :2; /* bandwidth control */ 00168 uint16_t MAJORLINKCH :6; /* enable channel-to-cannel link */ 00169 uint16_t DONE :1; /* channel done */ 00170 uint16_t ACTIVE :1; /* channel active */ 00171 uint16_t MAJORE_LINK :1; /* enable channel-to-channel link */ 00172 uint16_t E_SG :1; /* enable scatter/gather descriptor */ 00173 uint16_t D_REQ :1; /* disable IRQ request when done */ 00174 uint16_t INT_HALF :1; /* interrupt on citer = (biter >> 1) */ 00175 uint16_t INT_MAJ :1; /* interrupt on major loop completion */ 00176 uint16_t START :1; /* explicit channel start */ 00177 } P; 00178 struct 00179 { 00180 vuint32_t SETTINGS[8u]; 00181 } A; 00182 } TCD_t; 00183 /* 00184 ****************************************************************************** 00185 * Declarations 00186 *****************************************************************************/ 00187 /*** Extern ***/ 00188 00189 /*** Globals ***/ 00190 00191 /*** Static Globals ***/ 00192 00193 /* 00194 ****************************************************************************** 00195 * Function Prototypes 00196 *****************************************************************************/ 00197 /* 00198 ****************************************************************************** 00199 * 00200 * Function: vfnDMASet() 00201 * 00202 */ 00213 void vfnDMASet(uint8_t u8Chan, uint8_t *pu8DestAddr, uint8_t *pu8SourceAddr, 00214 uint16_t u16NOfBytes); 00215 /* 00216 ****************************************************************************** 00217 * 00218 * Function: vfnDMAConfig() 00219 * 00220 */ 00228 void vfnDMAConfig(TCD_t *ptMyTCD, uint8_t u8Channel); 00229 /* 00230 ****************************************************************************** 00231 * 00232 * Function: vfnDMAStart() 00233 * 00234 */ 00241 void vfnDMAStart(const uint8_t u8Chan); 00242 /* 00243 ****************************************************************************** 00244 * 00245 * Function: vfnDMAEnable() 00246 * 00247 */ 00254 void vfnDMAEnable(const uint8_t u8Chan); 00255 /* 00256 ****************************************************************************** 00257 * 00258 * Function: vfnDMAEnable() 00259 * 00260 */ 00267 uint8_t u8fnDMAPending(const uint8_t u8Chan); 00268 /* 00269 ****************************************************************************** 00270 * 00271 * Function: u8fnDMACopyArray() 00272 * 00273 */ 00283 void vfnDMACopyArray(uint8_t* pu8Source, uint8_t* pu8Target, uint16_t u16Size, 00284 uint8_t u8Channel); 00285 /* 00286 ****************************************************************************** 00287 * 00288 * Function: u8fnWaitForDMA() 00289 * 00290 */ 00298 uint8_t u8fnWaitForDMA(uint8_t u8Channel); 00299 /* 00300 ****************************************************************************** 00301 * 00302 * Function: u8fnDMAReturnChannelStatus() 00303 * 00304 */ 00311 uint8_t u8fnDMAReturnChannelStatus(uint8_t u8Channel); 00312 /* 00313 ****************************************************************************** 00314 * 00315 * Function: vfnDMAMUXInit() 00316 * 00317 */ 00329 void vfnDMAMUXInit(uint8_t u8DMACh, uint8_t u8DMAMuxSource, 00330 uint8_t u8Trigger, uint8_t u8Enable); 00331 /* 00332 ****************************************************************************** 00333 * 00334 * Function: vfnDMAMuxEnable() 00335 * 00336 */ 00344 void vfnDMAMuxEnable(uint8_t u8DMACh, uint8_t u8Enable); 00345 /* 00346 ****************************************************************************** 00347 * 00348 * Function: u8fnDMAMuxChEnStatus() 00349 * 00350 */ 00358 uint8_t u8fnDMAMuxChEnStatus(uint8_t u8DMACh); 00359 #endif /* _FILENAME_H */